Características principales
Test two 1.6T transceivers or an end-to-end high-speed interconnect using the dual OSFP ports
Full lifecycle validation for 1.6T, 800G and 400G across lab, fab and live environments
Superior hardware design: native OSFP interfaces, excellent signal quality, clean eye diagram and low error floor
Real-time FEC generation and analysis: testing of pre/post FEC BER, symbol error distribution and FEC margin
BLER: block error ratio statistics and efficient FLR estimation mechanism addresses time constraints of ultra-low BER measurements
PAM4 support for validating high-speed signaling performance
