Key features
Full lifecycle validation for 1.6T, 800G and 400G across lab, fab and live environments
Ensuring data integrity over ultra-fast connections and testing of pre/post FEC BER, symbol error distribution and FEC margin
High-level equalization capabilities to test challenged interconnects
Block error ratio (BLER) statistics and an efficient FLR estimation mechanism, addressing the time constraints of ultra-low BER measurements
Single RF SMPX connector supporting 8 channels at 212.5G and a dual RF SMPX supporting 16 channels at 212.5G—enabling parallel testing of BER/FEC/BLER
Streamline workflows, and reduce learning curves